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Name	Size	Permission	Date
amdgpu_drm.h	50.92 KB	-rw-r--r--	2026-06-30 10:53
amdxdna_accel.h	16.66 KB	-rw-r--r--	2026-06-30 10:53
armada_drm.h	1.18 KB	-rw-r--r--	2026-06-30 10:53
asahi_drm.h	35 KB	-rw-r--r--	2026-06-30 10:53
drm.h	46.54 KB	-rw-r--r--	2026-06-30 10:53
drm_fourcc.h	75.7 KB	-rw-r--r--	2026-06-30 10:53
drm_mode.h	40.83 KB	-rw-r--r--	2026-06-30 10:53
drm_sarea.h	2.72 KB	-rw-r--r--	2026-06-30 10:53
etnaviv_drm.h	11.71 KB	-rw-r--r--	2026-06-30 10:53
exynos_drm.h	10.87 KB	-rw-r--r--	2026-06-30 10:53
habanalabs_accel.h	79.61 KB	-rw-r--r--	2026-06-30 10:53
i915_drm.h	128.65 KB	-rw-r--r--	2026-06-30 10:53
ivpu_accel.h	14.41 KB	-rw-r--r--	2026-06-30 10:53
lima_drm.h	4.93 KB	-rw-r--r--	2026-06-30 10:53
msm_drm.h	20.71 KB	-rw-r--r--	2026-06-30 10:53
nouveau_drm.h	14.72 KB	-rw-r--r--	2026-06-30 10:53
nova_drm.h	2.03 KB	-rw-r--r--	2026-06-30 10:53
omap_drm.h	3.93 KB	-rw-r--r--	2026-06-30 10:53
panfrost_drm.h	8.94 KB	-rw-r--r--	2026-06-30 10:53
panthor_drm.h	31.11 KB	-rw-r--r--	2026-06-30 10:53
pvr_drm.h	39.22 KB	-rw-r--r--	2026-06-30 10:53
qaic_accel.h	11.79 KB	-rw-r--r--	2026-06-30 10:53
qxl_drm.h	4.03 KB	-rw-r--r--	2026-06-30 10:53
radeon_drm.h	37.34 KB	-rw-r--r--	2026-06-30 10:53
rocket_accel.h	3.75 KB	-rw-r--r--	2026-06-30 10:53
tegra_drm.h	21.13 KB	-rw-r--r--	2026-06-30 10:53
v3d_drm.h	23.8 KB	-rw-r--r--	2026-06-30 10:53
vc4_drm.h	14.12 KB	-rw-r--r--	2026-06-30 10:53
vgem_drm.h	1.92 KB	-rw-r--r--	2026-06-30 10:53
virtgpu_drm.h	7.88 KB	-rw-r--r--	2026-06-30 10:53
vmwgfx_drm.h	36.73 KB	-rw-r--r--	2026-06-30 10:53
xe_drm.h	77.43 KB	-rw-r--r--	2026-06-30 10:53

Rename

/* SPDX-License-Identifier: MIT */

#ifndef __NOVA_DRM_H__
#define __NOVA_DRM_H__

#include "drm.h"

/* DISCLAIMER: Do not use, this is not a stable uAPI.
 *
 * This uAPI serves only testing purposes as long as this driver is still in
 * development. It is required to implement and test infrastructure which is
 * upstreamed in the context of this driver. See also [1].
 *
 * [1] https://lore.kernel.org/dri-devel/Zfsj0_tb-0-tNrJy@cassiopeiae/T/#u
 */

#if defined(__cplusplus)
extern "C" {
#endif

/*
 * NOVA_GETPARAM_VRAM_BAR_SIZE
 *
 * Query the VRAM BAR size in bytes.
 */
#define NOVA_GETPARAM_VRAM_BAR_SIZE	0x1

/**
 * struct drm_nova_getparam - query GPU and driver metadata
 */
struct drm_nova_getparam {
	/**
	 * @param: The identifier of the parameter to query.
	 */
	__u64 param;

/**
	 * @value: The value for the specified parameter.
	 */
	__u64 value;
};

/**
 * struct drm_nova_gem_create - create a new DRM GEM object
 */
struct drm_nova_gem_create {
	/**
	 * @handle: The handle of the new DRM GEM object.
	 */
	__u32 handle;

/**
	 * @pad: 32 bit padding, should be 0.
	 */
	__u32 pad;

/**
	 * @size: The size of the new DRM GEM object.
	 */
	__u64 size;
};

/**
 * struct drm_nova_gem_info - query DRM GEM object metadata
 */
struct drm_nova_gem_info {
	/**
	 * @handle: The handle of the DRM GEM object to query.
	 */
	__u32 handle;

/**
	 * @pad: 32 bit padding, should be 0.
	 */
	__u32 pad;

/**
	 * @size: The size of the DRM GEM obejct.
	 */
	__u64 size;
};

#define DRM_NOVA_GETPARAM		0x00
#define DRM_NOVA_GEM_CREATE		0x01
#define DRM_NOVA_GEM_INFO		0x02

/* Note: this is an enum so that it can be resolved by Rust bindgen. */
enum {
	DRM_IOCTL_NOVA_GETPARAM		= DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GETPARAM,
						   struct drm_nova_getparam),
	DRM_IOCTL_NOVA_GEM_CREATE	= DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_CREATE,
						   struct drm_nova_gem_create),
	DRM_IOCTL_NOVA_GEM_INFO		= DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_INFO,
						   struct drm_nova_gem_info),
};

#if defined(__cplusplus)
}
#endif

#endif /* __NOVA_DRM_H__ */